In a conventional MOS transistor having a polycrystalline-silicon gate, both the gate dielectric and electrode layers are stacked directly on the planar surface of the silicon substrate as shown in FIGS. 1A and 1B. The heavily doped source and drain regions therefore must be profiled so that the junction interfaces are posited under the substrate surface. It has been previously reported by L. D. Yau, "A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's", page 1059 in Volume 17 of Solid State Electronics in 1974, and by G. Merckel, "Short Channels-Scaled Down MOSFET's", page 705 of "Process and Device Modeling for IC Design" edited by F. Van de Wiele et al. in 1977, that this conventional planar-MOS structure would have small geometry effects if the feature size of channel region were scaled down. See also S. M. Sze, Physics of Semiconductor Devices, pp. 469-509.
Also, to improve process control and to reduce dimension loss due to lateral diffusion, ion implantation is used to heavily dope the source and drain regions to a shallow junction depth. The implanted shallow junction, however, is deficient because of problems with the corner profile.
In addition, conventional processing is deficient where high circuit density is sought because the required alignment tolerance for the contact windows cannot be achieved. Unfortunately, it would be extremely expensive to fabricate a product not having these deficiencies using conventional planar MOS structure.
In order to overcome the problems of conventional MOS transistor fabrication for IC applications, the present invention describes an MOS transistor having a trench in the channel region. The now ancient U.S. Pat. No. 3,805,129 shows the gate of a field effect transistor deposited on the bottom of a trench. However, this reference does not show, among other things, the use of a polysilicon gate, a gate in the same plane as the source and drain regions, or doping to simlutaneously form a gate, source and drain region.
The trench structure can be etched by reactive ion etching as described in U.S. Pat. Nos. 4,139,442; 4,356,211; and 4,477,310. Theoretically, the MOS structure having the trench structure of the invention will have the advantage of less small-geometry effects because there is less overlapping charge between the depleted channel and the depleted source (and/or drain) regions.
Another advantage of the present invention is the ease of self-alignment of the heavily doped source and drain, and the polycrystalline silicon (polysilicon) gate electrode. This self-alignment also provides self-alignment of the contact between the conducting polysilicon lines and the source and drain regions. The self-alignment makes the dimension loss much less with the same feature size when a given photolithographic technique is performed.
The third advantage is that the shortcomings of shallow junction implantation due to the sharp concentration profile on junction corners in the conventional planar MOS structure is overcome. Deeper junction depth in source and drain doping is acceptable, thereby giving a better junction profile on the junction corners.